Synchronous LSI memory device

ABSTRACT

A synchronous LSI memory device, comprises memory cell array sections (BK 1,  BK 2 ) each having a plurality of memory cells; a timing generating section (CLOCK MASKED SECT) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to the status of a control signal (CKE); a signal generating section (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal after a predetermined number of accesses or in response to a stop signal (MRRST, MWSTP, LADA, BSTP); and a control section (SHIFT REGISTER) for controlling the cell array sections (BK 1,  BK 2 ) on the basis of outputs of the timing signal generating section and the signal generating section. In the synchronous LSI memory device, it is possible to operate the memory device whose access speed is lower than the CPU on the basis of a single high speed clock signal suitable for the CPU, so that it is possible to simplify the clock control so as to correspond to the higher speed CPU without complicating the system configuration.

FIELD OF THE INVENTION

The present invention relates to a synchronous LSI (large scale integrated circuit) device, and more specifically to a synchronous LSI memory device suitable for use with a high speed CPU.

BACKGROUND OF THE INVENTION

In general, in the case of a DRAM (Dynamic RAM) used as a main memory device of a computer, for instance, various control signals such as RAS (row access) signal, CAS (column access) signal, etc. are required. Conventionally, these control signals have been so far formed by processing a clock signal supplied as a signal for operating to the computer or CPU.

On the other hand, recently, the operating speed of the CPU has been improved to such an extent as to exceed that of the DRAM. Therefore, in a mini-computer or a work station composed of the CPU and the DRAM, the problem caused by the difference in operating speed between the two has been so far solved by use of the main memory constructed in the form of a plurality of banks (blocks) composed of DRAMs or in accordance with interleave operation of the memory. In this method of using the memory, however, the memory control procedure is complicated and thereby the cost of the memory increases inevitably.

On the other hand, another construction such that the memory is controlled internally in accordance with pipeline operation has been proposed. Where the memory is controlled in accordance with the simple pipeline operation, however, since the memory speed is determined by the data read speed from a core section, the pipeline method does not necessarily contribute to an improvement of the operating speed, so that a specific countermeasure must be taken for the memory control system to increase the memory speed to such an extent as to correspond to the CPU speed.

As described above, in the conventional synchronous LSI memory device, when the above-mentioned conventional memory operating methods such as interleave or bank switching, etc. are applied to a relatively small scale system such as a mini-computer or a work station, there exist problems in that the system cost is increased or down sizing is not attained. In addition, when the operating speed of the CPU is increased more and more as beyond 50 or 100 MHz, since the memory hierarchical structure must be constructed more ingeniously so as to use the CPU properly, with the result that the system is further complicated. For the reason as described above, there exists so far a strong need of memory structure and/or the memory control system which can match the operating speed of the CPU with that of the memory device.

SUMMARY OF THE INVENTION

With these problems in mind therefore, it is the object of the present invention to provide a synchronous LSI memory device which can correspond to a high speed CPU system, without complicating the system.

To achieve the above-mentioned object, the present invention provides a synchronous LSI memory device, comprising: memory cell array means (BK1, BK2) each having a plurality of memory cells; timing generating means (CLOCK MASKED SECT) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to status of a control signal (CKE); signal generating means (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal after a predetermined number of accesses OF in response to a stop signal (MRRST, MWSTP, LADA, BSTP); and control means (SHIFT REGISTER) for controlling said cell array means (BK1, BK2) on the basis of outputs of said timing signal generating means and said signal generating means.

Further, the present invention provides a synchronous LSI memory device, comprising: cell block means (CB) each having a plurality of memory cells; and data register means (WRITE REGISTER) for acquiring externally input data applied to first terminals (DQ) in synchronism with a clock signal (CLK), said data register means being provided with inputting registers (WRITE REGISTER) having a plurality of bits and connected to the respective first terminals; and when data are inputted, the inputting registers being controlled so that the respective plural bits are switched in sequence or not controlled so that the respective plural bits are set alternately to data input status.

Further, the present invention provides a synchronous LSI memory device, comprising: memory cell array means (BK1, BK2) each having a plurality of memory cells; timing generating means (TG) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to status of a control signal (CKE); signal generating means (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal (CP) after a predetermined number of accesses or in response to a stop signal (MRRST, MWSTP LADA, BSTP); control means for controlling said cell array means (BK1, BK2) on the basis of outputs of said timing signal generating means and said signal generating means (SERIAL SYS CONTROL); and mask control means (DQMR) for acquiring statuses of second terminals (DQM) in sequence into register means having the number of bits even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively to specific registers each having the number of bits even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the second terminals (DQM) are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal (CP).

In the synchronous LSI memory device according to the present invention, when a plurality of the cell array means (each having a plurality of memory cells) for a plurality of banks are accessed, the timing generating means generates the basic signal, and the signal generating means generates the second signals on the basis of the basic signal. The cell array means are controlled by the control means on the basis of the second signals.

Further, when data are inputted to a plurality of the cell array means (each having a plurality of memory cells) for a plurality of banks, the data register means acquire externally inputted data through the input register means connected to the DQ terminals of the data register means in synchronism with the clock signal CLK. In this case, the register means are so controlled as to input the external inputted data in sequence and further a plurality of bits of the register means are set alternately to the data input enable status when the data input sequence is not changed.

Further, when a plurality of the cell array means (each having a plurality of memory cells) for a plurality of banks are accessed, the statuses of the DQM terminals of the register means having the number of bits half of that of a word length are acquired in sequence, and the acquired data are outputted in sequence. The outputted data are inputted to the registers whose number of bits is half of that of a specific word, respectively. Further, when the data inputted through the DQM terminals are in the first status, the impedance control means outputs a signal for setting the output circuits of the register means to a high impedance status, on the basis of the basic signal outputted by the timing generating means and in synchronism with the second signals outputted by the signal generating means.

Accordingly, in the synchronous LSI memory device according to the present invention, it is possible to operate the memory device whose access speed is lower than the CPU on the basis of a single high speed clock signal suitable for the CPU, so that the it is possible to simplify the clock control so as to be correspond to the higher speed CPU without complicating the system configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing one embodiment of the memory device according to the present invention;

FIG. 2 is a circuit diagram showing a configuration of data lines of a 16M synchronous DRAM;

FIG. 3 is a circuit diagram showing an example of a configuration of a serial-system control section;

FIG. 4 is a circuit diagram showing another example of a configuration of the serial-system control section;

FIG. 5 is a partial circuit diagram showing a column activating detecting circuit;

FIG. 6 is a partial circuit diagram showing another column activation detecting circuit;

FIG. 7 is a circuit diagram showing a serial-system basic pulse generating circuit;

FIG. 8 is a circuit diagram showing a serial-system setting circuit;

FIG. 9 is a circuit diagram showing a column deactivation detecting circuit;

FIG. 10 is a circuit diagram showing a read mode detecting circuit;

FIG. 11 is a circuit diagram showing a write mode detecting circuit;

FIG. 12 is a circuit diagram showing a write latency detecting circuit;

FIG. 13 is a circuit diagram showing a tap address mode acquisition control circuit;

FIG. 14 is a circuit diagram showing a column cycle detecting circuit;

FIG. 15 is a circuit diagram showing a first shift register;

FIG. 16 is a circuit diagram showing a second shift register;

FIG. 17 is a circuit diagram showing a register group selecting circuit;

FIG. 18 is a circuit diagram showing a column-system basic signal generating circuit;

FIG. 19 is a circuit diagram showing a read register gating circuit;

FIG. 20 is a circuit diagram showing an XR register selection signal generating circuit;

FIG. 21 is a circuit diagram showing a used register group detecting circuit;

FIG. 22 is a circuit diagram showing a data transfer gating circuit;

FIGS. 23(A) and 23(B) are a circuit diagram showing a read data transferring circuit;

FIG. 24 is a circuit diagram showing a read data register circuit;

FIG. 25 is a circuit diagram showing a write register gating circuit;

FIG. 26 is a circuit diagram showing a data transfer selection signal generating circuit;

FIG. 27 is a circuit diagram showing a write data transfer signal generating circuit;

FIG. 28 is a circuit diagram showing a write data register circuit;

FIGS. 29(A) and 29(B) are a circuit diagram showing a first stage circuit for a serial system;

FIGS. 30(A) to 30(D) are a circuit diagrams showing an address buffer circuit;

FIGS. 31(A) and 31(B) are a circuit diagram showing a /WE buffer circuit;

FIG. 32 is a circuit diagram showing an address mode acquisition signal generating circuit;

FIG. 33 is a circuit diagram showing a read operation enabling circuit;

FIG. 34 is a circuit diagram showing a DQMR gating circuit;

FIG. 35 is a circuit diagram showing a high impedance control circuit;

FIG. 36 is a circuit diagram showing a DQMR register circuit;

FIG. 37 is a circuit diagram showing a RPRM generating circuit;

FIG. 38 is a circuit diagram showing a GDM generating circuit;

FIGS. 39(A) to 39(C) are a circuit diagram showing a DQM write register circuit;

FIG. 40 is a circuit diagram showing a DQM option circuit corresponding to the write latency;

FIG. 41 is a circuit diagram showing a short-period basic signal generating circuit;

FIG. 42 is a circuit diagram showing a register group detecting circuit;

FIGS. 43(A) to 43(D) are a circuit diagram showing a partial configuration for a module-length detection procedure selecting circuit;

FIGS. 44(A) and 44(B) are a circuit diagram showing another partial configuration for the module-length detection procedure selecting circuit;

FIG. 45 is a circuit diagram showing a module-length detecting circuit;

FIG. 46 is a circuit diagram showing a read module resetting circuit;

FIG. 47 is a circuit diagram showing a write module stopping circuit;

FIG. 48 is a circuit diagram showing a module-length detecting circuit;

FIG. 49 is a circuit diagram showing a module-number counting circuit;

FIG. 50 is a circuit diagram showing a burst stop command detecting circuit;

FIG. 51 is a circuit diagram showing a column-system bank switching circuit;

FIG. 52 is a circuit diagram showing a column-system selecting circuit;

FIG. 53 is a circuit diagram showing the column-system selecting circuit required when KI and KII signals are used as opposite phase signals /KI and /KII;

FIG. 54 is a circuit diagram showing a column decoder circuit;

FIG. 55 is a circuit diagram showing a column partial decoder;

FIG. 56 is a circuit diagram showing a spare CSL;

FIG. 57 is a circuit diagram showing a CSL driver;

FIG. 58 is a circuit diagram showing a CSL selector;

FIG. 59 is a circuit diagram showing a CSL selector driver;

FIG. 60 is a circuit diagram showing a CSL-related logic circuit;

FIGS. 61(A) to 61(E) are a circuit diagram showing a CLS select tap selection signal generating circuit;

FIGS. 62(A) to 62(C) are a circuit diagram showing an address-change basic pulse generating circuit;

FIG. 63 is a circuit diagram showing a counter driver circuit;

FIGS. 64(A) to 64(C) are a circuit diagram showing a spare select signal generating circuit;

FIG. 65 is a circuit diagram showing a partial decode S/N discriminate result acquisition signal generating circuit;

FIG. 66 is a circuit diagram showing a first part of an address counter circuit;

FIG. 67 is a circuit diagram showing a second part of the address counter circuit;

FIG. 68 is a circuit diagram showing a third part of the address counter circuit;

FIG. 69 is a circuit diagram showing a fourth part of the address counter circuit;

FIG. 70 is a circuit diagram showing a fifth part of the address counter circuit;

FIG. 71 is a circuit diagram showing a sixth part of the address counter circuit;

FIG. 72 is a circuit diagram showing a seventh part of the address counter circuit;

FIG. 73 is a circuit diagram showing a spare circuit;

FIG. 74 is a circuit diagram showing an (A1c=“1”)-side S/N discriminating circuit;

FIG. 75 is a circuit diagram showing an (A1c=“0”)-side S/N discriminating circuit;

FIG. 76 is an illustration for assistance in explaining the DQ buffer configuration of an 8-bit DRAM with two 1M-word banks;

FIG. 77 is an illustration for assistance in explaining the DQ buffer configuration of an 4-bit DRAM with two 2M-word banks;

FIG. 78 is a circuit diagram showing a DQ buffer activation signal detecting circuit;

FIG. 79 is a circuit diagram showing a QACT selecting circuit;

FIG. 80 is a circuit diagram showing a QACT selecting circuit;

FIG. 81 is a circuit diagram showing a QACT selecting circuit;

FIG. 82 is a circuit diagram showing an A9 counter circuit;

FIG. 83 is a circuit diagram showing an A9 counter circuit;

FIG. 84 is a circuit diagram showing an exemplary circuit for transferring data between the DQ buffer and a cell array;

FIGS. 85(A) and 85(B) are a circuit diagram showing a DQ line read control circuit;

FIG. 86 is a circuit diagram showing a DQ line write control circuit;

FIGS. 87(A) and 87(B) are a circuit diagram showing a DQ line read control circuit in an A9c and /A9c coexistent section;

FIG. 88 is a circuit diagram showing the DQ write control section configuration of the memory device shown in FIG. 1;

FIG. 89 is a timing chart showing the interleave bank read status in 4-wrap mode;

FIG. 90 is a timing chart showing the interleave bank read status in 8-wrap mode;

FIG. 91 is a timing chart showing the interleave bank write status in 8-wrap mode;

FIG. 92 is a timing chart showing the active page random read status in 4-wrap mode;

FIG. 93 is a timing chart for assistance in explaining the detailed operation of the embodiment according to the present invention;

FIG. 94 is a timing chart for assistance in explaining the detailed operation of the embodiment according to the present invention;

FIG. 95 is a timing chart for assistance in explaining the detailed operation of the embodiment according to the present invention;

FIG. 96 is a timing chart for assistance in explaining the detailed operation of the embodiment according to the present invention;

FIG. 97 is a timing chart for assistance in explaining the detailed operation of the embodiment according to the present invention;

FIG. 98 is a timing chart for assistance in explaining the detailed operation of the embodiment according to the present invention; and

FIG. 99 is a timing chart for assistance in explaining the detailed operation of the embodiment according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiment of the synchronous LSI memory device according to the present invention will be described hereinbelow with reference to the attached drawings.

Here, the terminology “latency” used in the specification and the drawings implies the number of clocks between when a command is inputted and when data are transferred in a synchronous device, which is widely employed in the field of the synchronous device.

Prior to the detailed description, the present invention will be summarized as follows: the synchronous LSI memory device of the present invention comprises: memory cell array means (BK1, BK2) each having a plurality of memory cells; timing generating means (CLOCK MASKED SECT) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to status of a control signal (CKE); signal generating means (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal after a predetermined number of accesses or in response to a stop signal (MRRST, MWSTP, LADA, BSTP); and control means (SHIFT REGISTER) for controlling said cell array means (BK1, BK2) on the basis of outputs of said timing signal generating means and said signal generating means (FIG. 4).

Further, the synchronous LSI memory device further comprises first means (SHIFT REGISTER) operative in response to the second signal (CP) to control access to said memory cell array means (BK1, BK2). The first means (SHIFT REGISTER) has the number of bits even-number times larger than that obtained during a cycle interval during which a column address is inputted, for activating column systems (COL SYS) of said memory cell array means (BK1, BK2) on the basis of specific output signals (K) of said first means (SHIFT REGISTER). Alternately, the first means (SHIFT REGISTER) comprises two-set independent shift registers (SHIFT 1, 2). Alternately, the first means (SHIFT REGISTER) changes an initial condition according to read latency.

Further, the synchronous LSI memory device of the present invention comprises: cell block means (CB) each having a plurality of memory cells; and data register means (WRITE REGISTER) for acquiring externally input data applied to first terminals (DQ) in synchronism with a clock signal (CLK), said data register means being provided with inputting registers (WRITE REGISTER) having a plurality of bits and connected to the respective first terminals; and when data are inputted, the inputting registers being controlled so that the respective plural bits are switched in sequence or not controlled so that the respective plural bits are set alternately to data input status (FIG. 61).

Further, a synchronous LSI memory device of the present invention comprises: memory cell array means (BK1, BK2) each having a plurality of memory cells; timing generating means (TG) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to status of a control signal (CKE); signal generating means (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal (CP) after a predetermined number of accesses or in response to a stop signal (MRRST, MWSTP LADA, BSTP); control means for controlling said cell array means (BK1, BK2) on the basis of outputs of said timing signal generating means and said signal generating means (SERIAL SYS CONTROL); and mask control means (DQMR) for acquiring statuses of second terminals (DQM) in sequence into register means having the number of bits even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively to specific registers each having the number of bits even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the second terminals (DQM) are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal (CP).

Further, the synchronous LSI memory device further comprises: data holding means (DQM WRITE REGISTER) for, in only write mode, acquiring the statuses of the second terminals (DQM) in synchronism with the second signal into registers having a plurality of bits in sequence and scrambling the acquired data on first data lines (DQMW) plural bits by plural bits every plural cycles; and precharge means (EQDQM) for precharging the first data lines into write disable status every predetermined cycle interval.

Here, when the predetermined access length is “1”, even-number registers of said data holding means (DQM WRITE REGISTER) are fixed to status the same as when masked data are acquired.

Further, the synchronous LSI memory device of the present invention further comprises: read mask registers (DQM READ REGISTER) for acquiring, in read mode, the statuses of the second terminals (DQM) into a plurality of registers in sequence in synchronism with the second signal, and outputting the acquired data to the data lines (DQMR) in sequence; and potential fixing means (/RPRM13, /RPRM24, HIZ) for fixing, in write mode, potentials of the data lines (DQMR) to set the output circuits connected to the data lines (DQMR) to a high impedance status (FIGS. 35 and 37).

Further, when the predetermined access length is “1”, even-number registers of said read mask registers having a bit number length half of a word length are fixed to a mask data output status. The stop signal (CLADA) is outputted subsequent to a predetermined number of accesses after all banks (BK1, BK2) have been precharged. Further, when the write latency is “1”, the stop signal (WRLA) is outputted in a first cycle immediately after write disable mode has been changed to write enable mode.

The number of predetermined accesses is counted on the basis of a signal (REG1, REG2) for selecting bits n-bits by n-bits by interleaving an m(=n+n)-bit register having two sets of n-bit registers (FIG. 17). Further, when a plurality of said cell block (CB) are accessed in series, a plurality of serially accessed cell blocks can be accessed simultaneously (FIG. 78). Further, when a plurality of said cell array means are accessed simultaneously, data buffers whose number is a half of that required when a single cell array is accessed are activated in the respective cell arrays means. Further, the second signal (CP) is divided into a plurality of signals (CPK, CPW, CPR) according to use so as to be controlled individually (FIG. 3).

FIG. 1 is a block diagram showing one embodiment of the synchronous LSI memory device, in particular which shows a configuration of a 2MX8 synchronous DRAM. In FIG. 1, a cell array is divided into a bank (I) BK1 and a bank (II) BK2, both of which are connected to a DQ buffer DQBF via a register RG. On the other hand, various signals such as /CS, /RAS, /CAS, /WE, DQM, CKE, CLK, etc. are inputted to a timing generator TG. For address control, a refresh counter RC, a row buffer RBF, a column counter CC, a precharge logic PLG, etc. are arranged. The banks BK1 and BK2 are selected by a bank select signal BS. The banks BK1 and BK2 are precharged by a bank I precharge PR1 and a bank II precharge PR2, respectively.

FIG. 88 shows the configuration of a DQ write control section used with the memory device shown in FIG. 1. In FIG. 88, a coexistent section of an address A9c and an address /A9c (an inverse signal of A9c) is shown.

The basic operation of the configuration shown in FIG. 88 will be described hereinbelow with reference to the timing charts shown in FIGS. 89, 90, 91 and 92. FIG. 89 is a timing chart showing the interleave bank read status in 4-wrap mode, FIG. 90 is a timing chart showing the interleave bank read status in B-wrap mode, FIG. 91 is a timing chart showing the interleave bank write status in 8-wrap mode, and FIG. 92 is a timing chart showing the active page random read status in 4-wrap mode.

In the synchronous LSI memory device, the array is activated in accordance with the bank active conditions listed in a truth table (See Table 1).

After the array activation, the mode is set to a read or write column active mode to operate the column system.

In the read mode, a series of data are outputted beginning from the cycle during which the column active conditions are designated, after a cycle for latency designated separately. In this case, the data length of a series of data is designated separately as a module length.

On the other hand, in the write mode, a series of data are inputted beginning from the cycle during which the column active conditions are designated. Here, in the read mode, the latencies are “1”, “2”, “3” and “4”, and the module lengths (page lengths) are “1”, “2”, “4” and “8”. Further, in the case of the write operation, there exists the case where a series of data are inputted after the latency of “1” (the succeeding cycle after the cycle during which the column active conditions are designated).

Further, in a series of data, there are different scrambles such as wrap mode or interleave mode. Tables 2 to 6 list the column-system activation sequence corresponding thereto. Table 2 lists the page wrap mode, Table 3 lists the 8-wrap mode, Table 4 lists the 8-interleave mode, Table 5 lists the 4-wrap mode, and Table 6 lists the 4-interleave mode, respectively (See Tables 4 to 6).

Here, when a series of data are being accessed, the column active conditions can be designated for each even number of cycles after the column active conditions have been designated. Further, a part or all of a series of the data can be masked. In the read mode, the DQM is set to a “H” level in response to a rise edge of the cycle clock one cycle before the cycle during which data are required to be masked. In the write mode, on the other hand, the DQM is set to the “H” level in response to a rise edge of the clock of the cycle during which the data required to be masked are acquired.

Further, the memory device is also provided with such a function that the inputted clock signal CLK is pretended to be not inputted by masking the inputted clock signal CLK. This function can be realized by setting the signal CKE to the “L” level in response to a rise edge of the clock signal CLK obtained one signal before the signal CLK required to be masked. Further, after the data of a designated module length have been accessed, it is possible to set the column active cycle to any given cycle.

Here, the operation of the column system and the serial-system will be described hereinbelow with reference to the block diagram shown in FIG. 2. FIG. 2 shows a configuration of one embodiment of the synchronous LSI memory device according to the present invention, in particular in which a configuration of the 16-M synchronous DRAM data lines is shown by way of example. As understood in FIG. 2, 4-bit length wire register and read register are provided for each DQ pin. These registers are connected to the DQ buffer via RWD lines, respectively. The DQ buffer is a circuit for transferring data to the cell array sections through the DQ lines.

FIG. 84 is a circuit diagram showing an exemplary circuit for transferring data between the DQ buffer and the cell array.

FIGS. 76 and 77 show the configuration of the DQ buffer, in which FIG. 76 shows the DQ buffer configuration of an 8-bit DRAM with two 1M-word banks and FIG. 77 shows the DQ buffer configuration of an 4-bit DRAM with two 2M-word banks. As shown in FIGS. 76 and 77, there are four DQ buffers on either side of each cell array, in which the DQ buffers arranged on both sides of the activated cell array are activated. The signals for activating the DQ buffers are QACT generated by DQ buffer activation signal generating circuit as shown in FIG. 78.

Column data are outputted to the DQ lines selectively from the column selected by the column select lines. With respect to the column select lines, appropriate two of the output signals CSLA to CSLH of the column decoder as shown in FIG. 54 are selected as the column select lines and further activated. In this case, the two selected column select lines are determined by scramble. The selected column select lines are controlled by the CSL selectors as shown in FIG. 58, the SCL selector drivers as shown in FIG. 59, the CSL-related logic circuits as shown in FIG. 60, the CLS select tap signal generating circuits as shown in FIG. 61, etc. Further, Table 7 lists the CSL select tap sets, and Table 8 lists the combination of the CSL selector operations (See Tables 7 and 8).

The serial system is operated by the circuits as shown in FIGS. 5 to 9. FIGS. 5 and 6 show column activation detecting circuits, respectively; FIG. 7 shows a serial-system basic pulse generating circuit; FIG. 8 shows a serial-system setting circuit; and FIG. 9 shows a column deactivation detecting circuit.

Further, DQM read registers and DQM write registers are incorporated to realize the word masking.

The DQM read registers receive the status of DQM in the order of “1”—“2”—“3”—“4”—“1” and latch the data. The latched dada are outputted to the DQMR lines. The DQMR lines are connected to the output buffer. When the DQM is at the “H” level, the output buffer is set to a high impedance status.

The DQM write registers operate in the same way as the write register. The obtained DQM status is outputted to the DQM lines two bits by two bits being scrambled. Before data are outputted from the DQM write registers, the DQMW lines are once precharged to the write disable status. Only when the “L” level DQM status is outputted to the DQMW lines, the data write is enabled.

The above-mentioned operation is controlled by the circuits as shown in FIGS. 33 to 40. FIG. 33 shows a read operation enabling circuit; FIG. 34 shows a DQMR gating circuit; FIG. 35 shows a high impedance control circuit; FIG. 36 shows a DQMR register circuit; FIG. 37 shows a RPRM generating circuit; FIG. 38 shows a GDM generating circuit; FIG. 39 shows a DQM write register circuit; and FIG. 40 shows a DQM option circuit corresponding to the write latency; respectively.

Further, the configuration of the read/write registers are shown in FIGS. 19 to 28. FIG. 19 shows a read register gate circuit; FIG. 20 shows an XR register selection signal generating circuit; FIG. 21 shows a used register group detecting circuit; FIG. 22 shows a data transfer gating circuit; FIG. 23 shows a read data transferring circuit; FIG. 24 shows a read data register circuit; FIG. 25 shows a write register gating circuit; FIG. 26 shows a data transfer selection signal generating circuit; FIG. 27 shows a write data transfer signal generating circuit; and FIG. 28 shows a write data register circuit, respectively.

The architecture, the serial operation, the word mask, the clock mask, the module length-related operation, the burst stop, the column system, the column-system address, the column-system data access of the present embodiment will be described herein below in sequence.

As shown in the serial operation explanation of Table 14, the functions required for the serial system of the SDRAM are such that: the serial system can correspond to the clock masking; column addresses can be inputted for each two cycles at minimum; the words can be masked; and the serial system is operated at 100 MHz.

To achieve the above-mentioned operation, it is necessary to access to the core section within a time of two cycles. In this case, a register is required to temporarily store the data read from the core section under consideration of the latency. To cope with the latency of “4”, the register requires 4 bit length at its minimum. By doing this, it is possible to prevent the interference between the present data and the new data read by the core section during the data outputting operation.

Further, since the column address can be changed for each two cycles, only 2-bit data of the 4-bit data can be a serial data at the same column address. Accordingly, it is necessary to handle a 4-bit register as two 2-bit registers; that is, data registers of 2+2 bit configuration are required.

As shown in the read mode and write mode operation explanation of Table 15, in the read mode, two system lines between the CLK signal and the RWD lines and between the RWD lines and the data registers are operated in pipeline mode to cope with a high speed operation. Therefore, it is necessary that the read-mode register interleaves the register group two bits by two bits to transfer data from the RWD lines to the registers for each two cycles. The data are outputted from the first register in sequence.

In contrast with this, in the write mode, it is necessary that the write-mode register interleaves the register group two bits by two bits to transfer data from the registers to the RWD lines for each two cycles. To execute the write operation at high speed, DQM lines are used. That is, before the write data are outputted to the RWD lines, the DQM lines are write-disabled. However, immediately when the write dada are outputted, the DQM lines are write-enabled, so that it is possible to execute the write operation at high speed without delaying the write operation.

FIG. 2 shows the circuit for realizing the above-mentioned operation at high speed.

Table 11 lists the architecture explanation of the serial-system configuration, which is adopted in accordance with the above-mentioned circuit configuration.

A basic signal CP is prepared to operate the serial system. This basic signal CP can be stopped in correspondence to the serial-system resetting and the write latency. Further, the basis signal CP is used to select shift registers for activating the data registers.

Further, it is necessary to operate the signal K for controlling the main access pass from the outputs of the shift registers to the core section, signals REG1 and REG2 for selecting a register group of two bit unit, and signal GDM for selecting the DQM registers, etc.

Further, the basis signal CP must cope with the clock masking (one of the functions). For the reason as mentioned above, the signal CP is formed on the basis of the synchronous signal CLK to be masked.

On the basis of the conditions as above, it is possible to adopt the serial-system architectures as shown in FIGS. 3 and 4. Here, FIGS. 3 and 4 show the configuration of the serial-system control lines, respectively. In FIG. 3, the basic signal CP is used for read, write, main pass activation signal K, etc. properly. On the other hand, in FIG. 4, only the shift registers are divided according to the uses, without separating the CP according to the uses. In the architectures shown in FIGS. 3 and 4, although the number of the required registers is different from each other, the number of registers activated simultaneously is the same in both.

The basic operation required for the respective sections will be described with reference to the architecture explanation of Table 12.

In the respective sections shown in FIGS. 3 and 4, the following operation is required.

The main pass activation signal K is enabled for each two cycles in synchronism with the basic signal CP, and further must be stopped when the serial system is stopped. Further, when the serial system is reset, this signal K is initialized so as to be enabled beginning from the first CLK signal. The read data register gate GR proceeds in synchronism with the basic signal CP. The serial system is reset so as to be restarted beginning from the read data register gate GRi corresponding to the read latency. This control corresponds to that the first access starts beginning from the read data register gate GR1. Further, in the write mode, the read data register gates are kept deactivated. The write register gate GW proceeds in synchronism with the basic signal CP. The serial system is reset so as to be restarted beginning from the write register gate GW1. Further, in the modes other than the write mode, the signals GW1 and GW3 are set to the “H” level and the signals GW2 and GW4 are set to the “L” level to read the first data.

The register group selection signal REG operates for each two cycles in synchronism with the basic signal CP, and is so set that when the serial system is reset, the succeeding operation starts beginning from the first register group. The DQM read register gates GDM proceed in synchronism with the basic signal CP, and some of these gates GDM are fixed at “L” or “H” level according to the read latency in modes other than the read mode. On the other hand, in the read mode, the DQM read register gates GDM operate in the same way as with the case of the data register gates GR.

The basic operation of the read corresponding sections will be described hereinbelow with reference to the architecture explanation of Table 13.

When the data are read from the core section, the data must be transferred to the read data registers. Further, after the normal data have been transferred to the read data registers, the read register gates must be so controlled as to be opened. For these operation, the data transfer signal XR is activated by the main pass activation signal K after the data have been read, and the read data register gates GR1 and GR3 are enabled after the data transfer signal XR has been activated.

Under the consideration as above, a serial-system control section as shown in FIG. 4 is adopted.

The basic operation in the read/write mode and the address acquisition will be described hereinbelow with reference to Table 16 to Table 18. Table 16 explains the read/write mode acquisition, the address acquisition, and the counter relationship; Table 17 explains the address signals used for the respective circuits in tap set; and Table 18 explains the write enable signal /WE used for the respective circuits.

The mode and the address are acquired in response to the first CLK signal in the column access cycle, and switched when the main pass activation signal K is deactivated at the “L” level. This is because the mode and the address must be switched only when the column system is being deactivated.

Further, the head address is set to an output prepare section of an address counter only when /R signal is set to the “H” level, except the module length is a page length. Here, the /R signal is set to the “H” level in the first cycle of the column access cycle, and to the “L” level when the main pass activation signal K changes to the “L” level. On the other hand, when the module length is the page length, the head address is set to the output section of the counter when the main pass activation signal falls.

Here, when the module length is other than the page length, the output section of the counter is opened only when the first main pass activation signal K after the column access cycle is at the “L” level, and kept closed in the other cases. On the other hand, when the module length is the page length, the output of the counter is counted up in response to a count-up signal.

Here, the basic operation of the serial-system setting or stopping operation will be described hereinbelow with reference to Table 19. Table 19 explains the serial-system enable.

In the read mode, the serial system is reset when the column access cycle will not start subsequent to the final data output cycle, after the cycles according to the latency. Further, the serial system is enabled after the succeeding column access cycle starts.

In the write mode, after the cycle in which the final data have been inputted, the serial system is stopped. Further, in the succeeding column access cycle, the serial system is enabled.

The above-mentioned operation can be achieved by the circuit configurations as shown in FIGS. 42 to 49. FIG. 42 shows a register group detecting circuit; FIG. 43 shows a partial configuration of a module-length detection procedure selecting circuit; FIG. 44 shows another partial configuration of the module-length detection procedure selecting circuit; FIG. 45 shows a module-length detecting circuit; FIG. 46 shows a read module resetting circuit; FIG. 47 shows a write module stopping circuit; FIG. 48 shows a module-length detecting circuit; and FIG. 49 shows a module-number counting circuit, respectively.

Further, when the write latency is “1”, the serial system is stopped for only first one cycle after the write mode starts from the mode other than the write mode. The above-mentioned operation can be operated by a write latency detecting circuit as shown in FIG. 12.

The mode detection required for the above-mentioned operation will be described hereinbelow with reference to Table 20.

The read mode or the write mode is detected in order to operate only the circuits required for the detected mode. Therefore, the mode is detected on the basis of a read detection signal READ or a write detection signal WRITE. These signals are generated by a read mode detecting circuit as shown in FIG. 10 and by a write mode detecting circuit as shown in FIG. 1.

The column cycle detection and the address mode acquisition of when the latency is “1” will be described hereinbelow with reference to Tables 21 and 22.

The detection of the column access cycle start of when the write latency is “1” is different from that of when the write latency is “0”. This is because the cycle during which the address mode is inputted is so controlled as to be delayed by one cycle from the cycle in which the address mode is actually used, as already explained. Therefore, when the mode is changed, it is necessary to detect the difference in latency. In this connection, when the latency is “0”, the above-mentioned discrimination is unnecessary.

In other words, when the latency is “0”, control is executed by a tap address mode acquisition control circuit as shown in FIG. 13. When the latency is “1”, on the other hand, control is executed by a column cycle detecting circuit as shown in FIG. 14 under detection of the cycle.

Further, a first shift register related to the serial system is configured as shown in FIG. 15, and a second shift register is configured as shown in FIG. 16, respectively. Further, the register group is selected by the configuration as shown in FIG. 17, and the column system basic signal can be generated by the configuration as shown in FIG. 18.

Further, with respect to the serial system operation, a first stage circuit as shown in FIG. 29, an address buffer circuit as shown in FIG. 30, a /WE buffer circuit as shown in FIG. 31, and an address mode acquisition signal generating circuit as shown in FIG. 32 are used, respectively.

The word masking operation will be explained with reference to Tables 23 and 24. Table 23 explains the word masking for the DQM read of when the latency is “4” and “3”; and Table 24 explains the work masking for the DQM high impedance of when the latency is “2”.

First, in the read mode, the latency of the word mask is “1”, and the read latency is not present. Further, for masking, it is regarded that the optimum way is to output high impedance data to the output buffers attached to the read data registers. The read data register can be configured by the circuit as shown in FIG. 24.

For this purpose, the respective outputs DQMRi of the DQM read registers as shown in FIGS. 35 and 36 are inputted to respective registers as shown in FIG. 24.

The outputs of the DQM read registers are signals for controlling the impedance (high or low) conditions of the outputs. Therefore, the DQM read registers must be controlled according to the read latency thereof, respectively. This is because the outputs thereof must be high impedance till the first access. The above-mentioned control is executed by the circuit configurations as shown in FIGS. 33 to 38.

The high impedance after the module will be described hereinbelow with reference to Table 25.

When the succeeding column cycle does not start for a time over the module length after the column activation cycle, the outputs are in high impedance state. However, since the serial system must be kept activated, high impedance conditions must be formed irrespective of the DQM values. Therefore, the high impedance must be kept for period of the module length+the latency CLK signal. The high impedance is released in dependence upon the latency by circuits as shown in FIGS. 35 and 36, respectively.

The DQM write will be described with reference to the explanation of Table 26.

The word masking in the write mode is executed in accordance with the method as already explained by circuits as shown in FIGS. 39 and 40. On the other hand, in the case where the write latency is “1”, the word masking is executed by circuits as shown in FIG. 40.

The clock masking will be described hereinbelow with reference to the explanation of Table 27.

In the clock masking, the operation is stopped in a cycle after the cycle in which the signal CKE is at the “L” level. To achieve this operation, the formation of a short period basic signal CPOR is controlled so as to be formed or not according to the status of the CKE signal acquired before one cycle. Further, the statuses of the CKE signals acquired before one cycle are inputted to the respective function detecting circuits except for that of the basic signal CP. When masking is required, the function detecting circuits are kept so as to be not set. The signal CPOR can be generated by a short period basic signal generating circuit as shown in FIG. 41.

The module length related operation will be described hereinbelow with reference to Tables 28 to 33. Table 28 explains the module length detecting operation; Table 29 explains the module operation and module reset releasing operation; Table 30 explains the module length detection resetting operation; Table 31 explains the summary of the module operation in the read and write modes; Table 32 explains the module status resetting operation; and Table 33 explains the column active cycle detecting operation and the operation corresponding to the module length of “1”, respectively.

In the read mode, the cycle in which the data of the module length are outputted can be set as the end of the module length. In the write mode, the cycle in which the data of the module length are inputted can be set as the end of the module length.

On the assumption as described above, in the read mode, the final data access begins from the read data register gate GR2 or GR4 on the basis of the register configuration. Further, since the register group for outputting the final data controls the read registers as already explained, the final data access is determined by only the module length, irrespective of the read latency.

The same can be applied to the case of the write mode.

In summary, it is possible to discriminate the register for implementing the final data access by detecting which register REG1 or REG2 is at the “L” level in the column access cycle. Since the module length is started to be counted for each column access cycle, the register is reset for each column access cycle. Further, in the case of the module length, when the counter (described later) is operated, the operation is the same as with the case where the module length is “8”. For the above-mentioned operation, circuits as shown in FIGS. 42 to 49 are adopted.

The burst stop will be described with reference to Table 34.

The burst stop operation is achieved by disabling the serial system in a cycle after the cycle in which a burst stop command is inputted during the burst cycle. In the above-mentioned burst stop operation, in order to stop the burst in any given burst cycle, a burst stop command detecting circuit as shown in FIG. 50 is used.

The operation of the column system will be described hereinbelow with reference to Table 35.

In the column system, a column system bank switching circuit as shown in FIG. 51 is applied. The entire switching circuit is controlled by the main pass activation signal K, and further the main pass activation signal K corresponding to the bank side activated in the column access cycle is also activated.

However, the main pass activation signal K not decoded on the basis of the bank designation signal is used for the other circuits not belonging to the respective banks.

The column system is so configured as to provide the scramble; that is, so as to correspond to an addressing mode, which is one of the features of the SDRAM. Tables 2 to 6 list how to change the lower order significant address bits and how to activate the column select lines, the DQ buffers and the data registers according to the change in the lower order significant address bits in correspondence to the scramble.

In the respective tables, the portions divided by arrows, respectively correspond to two clock signals CLK in the one-bit lower cycle K. Further, the register scramble implies the way of selecting the transfer signals when data are transferred to or from the data registers shown in FIGS. 23 or 26. Further, in the respective tables, although the addresses of the lower bits A0, A1 and A2 are explained, the addresses higher than A3 can be decoded by the column address decoder as shown in FIG. 54. This column decoder is decoded by a column partial decoder as shown in FIG. 55. Further, in order to realize the operation of the column select lines as listed in Tables 2 to 6, the circuits as shown in FIGS. 56 to 61 are applied. FIG. 56 shows a spare CSL and FIG. 57 shows a CSL driver, respectively.

The column system address will be described hereinbelow with reference to Table 36.

With respect to the column address, the addresses are generated or the spare circuit is operated by the configurations as shown in FIGS. 62 to 75. FIG. 62 shows an address-change basic pulse generating circuit; FIG. 63 shows a counter driver circuit; FIG. 64 shows a spare select signal generating circuit; FIG. 65 shows a partial decode S/N discriminate result acquisition signal generating circuit; FIG. 66 shows a first part of the address counter circuit; FIGS. 67 to 72 show the other address counter circuits; FIG. 73 shows a spare circuit; FIG. 74 shows an (A1c=“1”)-side S/N discriminating circuit; and FIG. 75 shows an (A1c=“0”)-side S/N discriminating circuit, respectively.

First, the counter generates column addresses at which the partial decode signals are changed for each 8 cycles in the page mode. In the modes other than the page mode, since no count-up operation by the counter is required, it is unnecessary to transmit a carry. Therefore, in the page mode, a head address is set to the counter output on the basis of a signal CLSETP in the column access cycle. In the burst cycle, the counter begins to operate between the fifth cycle and the eighth cycle after the column access cycle.

The count-up cycle in the burst cycle in the page mode can be detected by a circuit as shown in FIG. 62, and the counter is directly driven by a circuit as shown in FIG. 63. The counters are connected as shown in FIG. 66, and the counters are configured as shown in FIGS. 67 to 72, respectively for implementing the desired address counting operation.

In the page mode, the column spare circuit executes the spare/normal discrimination without delay caused by the spare circuit operation. For this purpose, the address counter is first operated; a spare address is compared with an address outputted next; and the address is discriminated before the actual address is used. Further, in the page mode, the column decoder corresponding to the head address and the column decoder corresponding to the next address are both activated. Therefore, one of the discriminated results of both the decoders is determined by a circuit as shown in FIG. 64.

The switching of the partial decode signals and the S/N discrimination result acquisition by the column system address will be described hereinbelow with reference to Table 37.

The spare/column discrimination signal and the column partial decode signal are changed at 8 cycle intervals after the column access cycle. The spare/normal discriminating circuit is connected to another circuit, as shown in FIG. 73, and configured as shown in FIGS. 74 and 75. In the modes other than the page mode, since the column decoders will not be changed in the burst cycle, a switching signal as shown in FIG. 65 is kept at a constant value.

The switching operation between 4-bit and 8-bit in the column system data access will be described hereinbelow with reference to Tables 38 to 40. Table 38 the change between X4 and X8 and the decode of A9c in the X4; Table 39 explains the X4 page; and Table 40 explains the QACT control and the A9c control, respectively.

FIG. 76 shows the addresses and the output numbers corresponding to the respective cell arrays in the 8-bit, and FIG. 77 shows the addresses and the output numbers corresponding to the respective cell arrays in the 4-bit, respectively. To switch X8 to X4 or vice versa, the connection between the RWD lies and the DQ buffers are changed as listed in Table 9.

First, when the X8 is switched to the X4, the signal QACT for activating the DQ buffer is decoded. In the case of the page length of X4, as listed in Table 10, there exists the case where the two cell arrays are accessed. In this case, however, the QACT0 and QACT3 are both activated securely.

The signals QACT0 exist in the cell arrays to be accessed subsequently and the signals QACT3 exist in the cell arrays to be accessed previously. Therefore, the addresses A9c of the cell arrays to be accessed previously and subsequently are latched, and the timings at which two cell arrays are accessed are detected. These operations are executed by the circuits as shown in FIGS. 79 to 83. Here, FIGS. 79, 80 and 81 show QACT selecting circuits; FIG. 82 shows an A9 counter; and FIG. 83 shows an A9 counter driving circuit, respectively.

Further, FIG. 84 shows a DQ buffer; FIG. 85 shows a DQ line read control circuit;

FIG. 86 is a circuit diagram showing a DQ line write control circuit; FIG. 87 shows a DQ line read control circuit in an A9c and /A9c coexistent section; and FIG. 88 shows a DQ write control circuit of in the A9c and /A9c co-existent section.

Further, the column system bank switching is executed by a circuit as shown in FIG. 51, and the column system selection is executed by a circuit as shown in FIG. 52. Further, when the KI/KII are used as the opposite phase signals, a circuit as shown in FIG. 53 is used.

The detailed operation of the embodiment according to the present invention is explained in timing charts shown in FIGS. 93 to 99. FIG. 93 shows the operation obtained when the latency is “2” and the module length is “4”; FIG. 94 shows the operation obtained when the latency is “3” and the module length is “4”; and FIG. 95 shows the operation obtained when the latency is “4” and the module length is “4”, respectively. In these timing charts, there are shown various signals CLK, /CAS, DQM, CLKIN, CPOR, CP, /SF11, /SF12, /DF13, /SF14, /SF21, /SF22, /SF23, /SF24 /REG1, REG2, K, CFP, RLL, WMR1, WMR2, HiZ, /RPRMij, GDM1, GDM2, GDM3, GDM4, DQMR1, DQMR2, DQMR3, DQMR4, GR1, GR2, GR3, GR4, R, CLSET, DQ, etc., respectively. Further, FIG. 96 shows the operation obtained when the latency is “2”, the module length is “4” and the write latency is “0”; FIG. 97 shows the operation obtained when the latency is “3”, the module length is “4” and the write latency is “0”; and FIG. 98 shows the operation obtained when the latency is “4”, the module length is “4” and the write latency is “0”, respectively. In these timing charts, there are shown various signals such as CLK, /CAS, /WE, COLACT, /NONCLA, CLKIN, CPOR, CP, READ, WRITE, /R, CLSET, /SF11, /SF12, /DF13, /SF14, /SF21, /SF22, /SF23, /SF24, REG1, REG2, K, /PERM, GR1, GR2, GR3, GR4, GW1, GW2, GW3, GW4, REG110, REG101, REG210, REG201, XR110, XR101, XR210, XR201, /XW, RWDin, DQn, CFP, RiL, WMRi, /RMR, MRRST, SRST, Hi-Z, etc., respectively. Further, FIG. 99 shows the operation obtained when the page mode is (X4) and the tap=9, in which there are shown various signals such as CLK, K, KR, PLS1, PLS2, PLS3, PLS4, CNTF, /CNTB, CNTP, /PX, /PY, /PX, X, Y, /YCHAN, ACi, SA to SD, SE to SH, Kp, Kp′, SAB, SBC, SCD, SDE, SEF, SFG, SGH, SHA, TA/B/C, /CDRVA, /CDRVB, /CDRVC, /CDRVD, /CDRVE, /CDRVF, /CDRVG, /CDRVH, /CNT9, /ACL9, /QA9C, ALGi, QACT00, QACT01, QACT02, QACT03, QACT10. QACT11, QACT12, QACT13, etc., respectively.

As understood by the above-mentioned embodiment, the present invention provides the synchronous LSI memory device as follows:

(1) The basic signal synchronous with the CKE signal related to the mask is generated according to the status of the CKE signal, and the memory device is accessed on the basis of the second signals stopped after the previously determined number of accesses has been made or when the stop signal is inputted.

(2) Further, in the configuration of (1), the initial operation is executed by the shift registers accessed on the basis of the second signal.

(3) Further, with the use of the 4-bit shift registers of the configuration of (2), the column system is activated on the basis of the outputs of the specific shift registers.

(4) Further, the two sets of the shift registers of the configuration of (2) are incorporated.

(3) Further, in the configuration of (2), the initial conditions are changed according to the read latency.

(6) The shift registers for acquiring externally inputted data in synchronism with the CLK signal are provided. Further, 4-bit input registers are provided for each DQ pin. The data input is so controlled that data can be inputted to the input registers in sequence. When the data input sequence is not changed, the alternate two-bit registers are provided for inputting data.

(7) The DQM status is acquired by the 4-bit registers in sequence. The acquired data are outputted in sequence, and the outputted data are inputted to the specific 4-bit registers, respectively. When the inputted DQM data is in the first status, the 4-bit registers generate a signal for setting the output circuits thereof to a high impedance status in synchronism with the second signal of the configuration of (1).

(8) The data registers for acquiring the DQM by the 4-bit registers in sequence in synchronism with the second signal only in the write mode are provided. The data of the registers are outputted to the DQMW lines two bits by two bits for each two cycles under scrambling condition, and the DQMW lines are precharged at predetermined cycle intervals.

(9) When the predetermined access length is “1”, the second and fourth register values of the 4-bit length DQM write registers are fixed in the same status as when the masked data are acquired.

(10) The data registers for acquiring the DQM in the 4-bit registers in sequence in synchronism with the second signal in the read mode are provided. The data of these data registers are outputted in sequence to the DQMW lines. In the write mode, the DQMW lines are fixed in a high impedance status by an output circuits.

(11) When the predetermined access length is “1”, the second and fourth outputs of the 4-bit length DQM read registers are fixed in the mask data outputting status.

(12) In the configuration of (1), the stop signals are outputted subsequent to the two bank precharge, after a predetermined number of accesses has been completed.

(13) Further, when the write latency is “1” in the configuration of (1), the stop signal is outputted between the non-write status and the first cycle in the write mode.

(14) The previously determined number of cycles is counted on the basis of signals selected two bits by two bits by interleaving the 4(2+2)-bit registers.

(15) When a plurality of cell arrays are serial-accessed, the serial access is so controlled that a plurality of cell arrays are accessed simultaneously.

(16) In the configuration of (15), when the a plurality of cell arrays are accessed simultaneously, the DQ buffers whose number is half that accessed separately are activated.

(17) In the configuration of (1), the second signals are divided into a plurality of signals according to the uses, for instance as CPK, CPW, CPR, etc. in FIG. 3, so as to be controlled respectively.

As describe above, in the synchronous LSI memory device according to the present invention, the cell arrays are divided into two banks; there are provided the timing generators for generating accessing signals in synchronism with the masked CLK signal; the column systems of the two-band cell arrays are pipeline-operated via DQ buffers and registers so that an access can be made once between the core sections for each two clocks. Further, in the read mode, the data read from the core section are transferred being interleaved to the 4-bit serial registers two bits by two bits, and the data transferred to the serial registers are outputted in series. In the write mode, data are read to the serial registers in sequence, the read data are written being interleaved in the core sections two bit by two bits.

As a result, it is possible to operate both the CPU operative in response to a high speed clock signal and the memory device operative in response to a low speed on the basis of the same single clock, thus realizing a synchronous LSI memory device which can be incorporated in a high speed CPU, without complication of the system.

As described above, in the synchronous LSI memory device according to the present invention, it is possible to operate the memory device whose access speed is lower than the CPU on the basis of a single high speed clock signal suitable for the CPU, so that the it is possible to simplify the clock control so as to be correspond to the higher speed CPU without complicating the system configuration.

TABLE 1 1) Truth table. 1. CKE is active high. 2. CBR and Self-Refresh Entry are other commands on CL level 3. CBR becomes auto-precharge. 4. Auto precharge by A10 is added to read/write operation. 5. CKE suspends clocks for inputting all command and inputting and outputting data. TRUTH TABLE COMMAND CKE DQM BS A10 A90 /CS /PAS /CAS /WE MNEMONIC MODE REG SET H² X V V V L L L L MRS CBR & AUTO-PRECHG H² X X X X L L L H REFR SELF-REFRESH ENTRY L¹ X X X X L L L H SREF BANK DEACTV/PRECHG H² X V L X L L H L DEAC PRECHG ALL H² X X H X L L H L PALL BANK ACTV H² X V V V L L H H ACTV WRITE H² X V L V L H L L WRIT WRITE & AUTO-PRECHG H² X V H V L H L L WRIT A READ H² X V L V L H L H READ READ & AUTO-PRECHG H² X V H V L H L H READ A RESERVED H² X X X X L H H L NOP1 RESERVED H² X X X X L H H H NOP2 DEVICE-DESELECT H² X X X X H X X X DSEL CLK SUS/STDBY MODE L² X X X X X X X X HOLD DATA WR/OUT ENABLE H² L X X X X X X X ENBL DATA MSK/OUT DISBL H² H X X X X X X X MASK (1) CKE status is H level in same cycle/previous cycle. (2) CKE status is previous cycle. (3) V = Valid X = Don't care L = Low H = High (4) All inputs are acquired by rise edges of CLK. (5) MRS, REFR and SREF are executed when two banks are precharged.

TABLE 1 1) Truth table. 1. CKE is active high. 2. CBR and Self-Refresh Entry are other commands on CL level 3. CBR becomes auto-precharge. 4. Auto precharge by A10 is added to read/write operation. 5. CKE suspends clocks for inputting all command and inputting and outputting data. TRUTH TABLE COMMAND CKE DQM BS A10 A90 /CS /PAS /CAS /WE MNEMONIC MODE REG SET H² X V V V L L L L MRS CBR & AUTO-PRECHG H² X X X X L L L H REFR SELF-REFRESH ENTRY L¹ X X X X L L L H SREF BANK DEACTV/PRECHG H² X V L X L L H L DEAC PRECHG ALL H² X X H X L L H L PALL BANK ACTV H² X V V V L L H H ACTV WRITE H² X V L V L H L L WRIT WRITE & AUTO-PRECHG H² X V H V L H L L WRIT A READ H² X V L V L H L H READ READ & AUTO-PRECHG H² X V H V L H L H READ A RESERVED H² X X X X L H H L NOP1 RESERVED H² X X X X L H H H NOP2 DEVICE-DESELECT H² X X X X H X X X DSEL CLK SUS/STDBY MODE L² X X X X X X X X HOLD DATA WR/OUT ENABLE H² L X X X X X X X ENBL DATA MSK/OUT DISBL H² H X X X X X X X MASK (1) CKE status is H level in same cycle/previous cycle. (2) CKE status is previous cycle. (3) V = Valid X = Don't care L = Low H = High (4) All inputs are acquired by rise edges of CLK. (5) MRS, REFR and SREF are executed when two banks are precharged.

TABLE 3 (Column system activation sequence) (8-WRAP) TAP ADD SEQ CSL SEQ DQ ACTV SEQ ADD SCR'BLE 0 01234567 AB→AB→CD→CD 01→23→01→23 01→01→01→01 01 EF→EF→GH→GH 1 12345670 AB→BC→CD→DA 12→30→12→30 10→10→10→10 10 EF→FG→HE→HE 2 23456701 BC→BC→DA→DA 23→01→23→01 01→01→01→10 01 FG→FG→HE→HE 3 34567012 BC→CD→DA→AB 30→12→30→12 10→10→10→10 10 FG→GH→HE→EF 4 45670123 CD→CD→AB→AB 01→23→01→23 01→01→01→01 01 GH→GH→EF→EF 5 56701234 CD→DA→AB→BC 12→30→12→30 10→10→10→10 10 GH→HE→EF→FG 6 67012345 DA→DA→BC→BC 23→01→23→01 01→01→01→01 01 HE→HE→FG→FG 7 70123456 DA→AB→BC→CD 30→12→30→12 10→10→10→10 10 HE→EF→FG→GH

TABLE 3 (Column system activation sequence) (8-WRAP) TAP ADD SEQ CSL SEQ DQ ACTV SEQ ADD SCR'BLE 0 01234567 AB→AB→CD→CD 01→23→01→23 01→01→01→01 01 EF→EF→GH→GH 1 12345670 AB→BC→CD→DA 12→30→12→30 10→10→10→10 10 EF→FG→HE→HE 2 23456701 BC→BC→DA→DA 23→01→23→01 01→01→01→10 01 FG→FG→HE→HE 3 34567012 BC→CD→DA→AB 30→12→30→12 10→10→10→10 10 FG→GH→HE→EF 4 45670123 CD→CD→AB→AB 01→23→01→23 01→01→01→01 01 GH→GH→EF→EF 5 56701234 CD→DA→AB→BC 12→30→12→30 10→10→10→10 10 GH→HE→EF→FG 6 67012345 DA→DA→BC→BC 23→01→23→01 01→01→01→01 01 HE→HE→FG→FG 7 70123456 DA→AB→BC→CD 30→12→30→12 10→10→10→10 10 HE→EF→FG→GH

TABLE 5 16M synchronous DRAM (Column system activation sequence) (4-WRAP) TAP ADD SEQ CSL SEQ DQ ACTV SEQ ADD SCR'BLE 0 0 1 2 3 AB→AB/CD→CD 01→23 01→01 01 EF→EF/GH→GH 1 1 2 3 0 AB→AB/CD→CD 12→30 10→10 10 EF→EF/GH→GH 2 2 3 0 1 AB→AB/CD→CD 23→01 01→01 01 EF→EF/GH→GH 3 3 0 1 2 AB→AB/CD→CD 30→12 10→10 10 EF→EF/GH→GH

TABLE 5 16M synchronous DRAM (Column system activation sequence) (4-WRAP) TAP ADD SEQ CSL SEQ DQ ACTV SEQ ADD SCR'BLE 0 0 1 2 3 AB→AB/CD→CD 01→23 01→01 01 EF→EF/GH→GH 1 1 2 3 0 AB→AB/CD→CD 12→30 10→10 10 EF→EF/GH→GH 2 2 3 0 1 AB→AB/CD→CD 23→01 01→01 01 EF→EF/GH→GH 3 3 0 1 2 AB→AB/CD→CD 30→12 10→10 10 EF→EF/GH→GH

TABLE 5 16M synchronous DRAM (Column system activation sequence) (4-WRAP) TAP ADD SEQ CSL SEQ DQ ACTV SEQ ADD SCR'BLE 0 0 1 2 3 AB→AB/CD→CD 01→23 01→01 01 EF→EF/GH→GH 1 1 2 3 0 AB→AB/CD→CD 12→30 10→10 10 EF→EF/GH→GH 2 2 3 0 1 AB→AB/CD→CD 23→01 01→01 01 EF→EF/GH→GH 3 3 0 1 2 AB→AB/CD→CD 30→12 10→10 10 EF→EF/GH→GH

TABLE 5 16M synchronous DRAM (Column system activation sequence) (4-WRAP) TAP ADD SEQ CSL SEQ DQ ACTV SEQ ADD SCR'BLE 0 0 1 2 3 AB→AB/CD→CD 01→23 01→01 01 EF→EF/GH→GH 1 1 2 3 0 AB→AB/CD→CD 12→30 10→10 10 EF→EF/GH→GH 2 2 3 0 1 AB→AB/CD→CD 23→01 01→01 01 EF→EF/GH→GH 3 3 0 1 2 AB→AB/CD→CD 30→12 10→10 10 EF→EF/GH→GH

TABLE 5 16M synchronous DRAM (Column system activation sequence) (4-WRAP) TAP ADD SEQ CSL SEQ DQ ACTV SEQ ADD SCR'BLE 0 0 1 2 3 AB→AB/CD→CD 01→23 01→01 01 EF→EF/GH→GH 1 1 2 3 0 AB→AB/CD→CD 12→30 10→10 10 EF→EF/GH→GH 2 2 3 0 1 AB→AB/CD→CD 23→01 01→01 01 EF→EF/GH→GH 3 3 0 1 2 AB→AB/CD→CD 30→12 10→10 10 EF→EF/GH→GH

TABLE 10 /CDRV PRE NEW ADDRESS SHIFT REG AC9 AC9 TAP SEQ SEQ QACT SEQ TYPE LAST START COEXIST 0 01234567 AB→BC→CD→DE 01→23→01→23 A HA AB EF→FG→GH→HA 01→23→01→23 1 12345670 AB→BC→CD→DE 12→30→12→30 B GH AB HA EF→FG→GH→HA 12→30→12→30 2 23456701 BC→CD→DE→EF 23→01→23→01 / HA AB FG→GH→HA→AB 23→01→23→01 A 3 34567012 BC→CD→DE→EF 30→12→30→12 / GH AB HA FG→GH→HA→AB 30→12→30→12 B 4 45670123 CD→DE→EF→FG 01→23→01→23 A HA AB GH→HA→AB→BC 01→23→01→23 I 5 56701234 CD→DE→EF→FG 12→30→12→30 B GH AB HA GH→HA→AB→BC 12→30→12→30 6 67012345 DE→EF→FG→GH 23→01→23→01 / HA AB HA→AB→BC→CD 23→01→23→01 A 7 70123456 DE→EF→FG→GH 30→12→30→12 / GH AB HA HA→AB→BC→CD 30→12→30→12 B A9c change side

TABLE 10 /CDRV PRE NEW ADDRESS SHIFT REG AC9 AC9 TAP SEQ SEQ QACT SEQ TYPE LAST START COEXIST 0 01234567 AB→BC→CD→DE 01→23→01→23 A HA AB EF→FG→GH→HA 01→23→01→23 1 12345670 AB→BC→CD→DE 12→30→12→30 B GH AB HA EF→FG→GH→HA 12→30→12→30 2 23456701 BC→CD→DE→EF 23→01→23→01 / HA AB FG→GH→HA→AB 23→01→23→01 A 3 34567012 BC→CD→DE→EF 30→12→30→12 / GH AB HA FG→GH→HA→AB 30→12→30→12 B 4 45670123 CD→DE→EF→FG 01→23→01→23 A HA AB GH→HA→AB→BC 01→23→01→23 I 5 56701234 CD→DE→EF→FG 12→30→12→30 B GH AB HA GH→HA→AB→BC 12→30→12→30 6 67012345 DE→EF→FG→GH 23→01→23→01 / HA AB HA→AB→BC→CD 23→01→23→01 A 7 70123456 DE→EF→FG→GH 30→12→30→12 / GH AB HA HA→AB→BC→CD 30→12→30→12 B A9c change side

TABLE 12

TABLE 13

TABLE 14 [SERIAL OPERATION EXPLANATION] (See FIGS. 5 to 32)

TABLE 15

TABLE 16

TABLE 17 ADDRESS SIGNALS USED FOR CIRCUITS (IN TAP SET)

TABLE 18

TABLE 19

TABLE 19

TABLE 21

TABLE 22

TABLE 23 [word mask EXPLANANTION (See FIGS. 33 to 40)

TABLE 24

TABLE 25

TABLE 26

TABLE 27 [CLOCK MASK EXPLANATION] (See FIG. 41)

TABLE 27 [CLOCK MASK EXPLANATION] (See FIG. 41)

TABLE 29

TABLE 30

TABLE 30

TABLE 32

TABLE 33

TABLE 34 [BURST STOP EXPLANATION] (See FIG. 50)

TABLE 35 [COLUMN SYS EXPLANATION] (See FIGs. 51 to 6 and Tables 2 to 8)

TABLE 35 [COLUMN SYS EXPLANATION] (See FIGs. 51 to 6 and Tables 2 to 8)

TABLE 37

TABLE 37

TABLE 39

TABLE 40 

What is claimed is:
 1. A synchronous LSI memory device supplied with a clock signal, a stop signal and a control signal, comprising: memory cell array means each having a plurality of memory cells; timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal; signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means; mask control means for acquiring statuses of terminals in sequence into register means having a number of bits that are an even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively, to specific registers each having the number of bits that are an even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the terminals are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal; data holding means for, in only a write mode, acquiring the statuses of the terminals in synchronism with the second signal into registers having a plurality of bits in sequence and scrambling the acquired data on first data lines plural bits by plural bits every plural cycles; and precharge means for precharging the first data lines into a write disable status every predetermined cycle interval, said data holding means and said precharge means being activated in the write mode.
 2. The synchronous LSI memory device of claim 1, wherein when a predetermined access length is “1”, even-number registers of said data holding means are fixed to a status that is the same as when masked data are acquired.
 3. A synchronous LSI memory device supplied with a clock signal, a stop signal and a control signal, comprising: memory cell array means each having a plurality of memory cells; timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal; signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means; mask control means for acquiring statuses of terminals in sequence into register means having a number of bits that are an even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively, to specific registers each having the number of bits that are an even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the terminals are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal; read mask registers for acquiring, in a read mode, the statuses of the second terminals into a plurality of registers in sequence in synchronism with the second signal, and outputting the acquired data to data lines in sequence; and potential fixing means for fixing, in a write mode, potentials of the data lines to set output circuits connected to the data lines to a high impedance status.
 4. The synchronous LSI memory device of claim 3, wherein when a predetermined access length is “1”, even-number registers of said read mask registers having a bit number length half of a word length are fixed to a mask data output status.
 5. A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising: memory cell array means each having a plurality of memory cells; timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal; signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; and control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means, wherein the stop signal is outputted subsequent to a predetermined number of accesses of the memory cells after the memory cells have been precharged by a precharge means.
 6. The synchronous LSI memory device of claim 5, wherein when a write latency is “1”, the stop signal is outputted in a first clock cycle immediately after a write disable mode has been changed to a write enable mode.
 7. A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising: memory cell array means each having a plurality of memory cells; timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal; signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; and control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means, wherein the number of predetermined accesses is counted on the basis of a signal for selecting bits n-bits by n-bits by interleaving an m(=n+n)-bit register having two sets of n-bit registers.
 8. A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising: memory cell array means each having a plurality of memory cells; timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal; signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; and control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means, wherein when a plurality of said memory cells are accessed in series, a plurality of serially accessed memory cells can be accessed simultaneously.
 9. The synchronous LSI memory device of claim 8, wherein when a plurality of said cell array means are accessed simultaneously, a plurality of data buffers whose number is a half of that required when a single cell array is accessed are activated in the respective cell arrays means.
 10. A synchronous LSI memory device supplied with a clock signal, a stop signal, and a control signal, comprising: memory cell array means each having a plurality of memory cells; timing generating means for generating a first basic signal synchronous with the clock signal and masked according to status of the control signal; signal generating means for generating a second signal in synchronism with the first basic signal and stopping generating the second signal after a predetermined number of accesses of the memory cells or in response to the stop signal; and control means for controlling said memory cell array means on the basis of outputs of said timing generating means and said signal generating means, wherein the second signal is divided into a plurality of signals according to use so as to be controlled individually.
 11. A synchronous memory device operable in response to a clock signal, bank select address signals, address signals, /CS (inverted Chip Select Signal), /RAS (inverted Row Address Strobe signal), /CAS (inverted Column Address Strobe signal) and /WE (inverted Write Enable signal), and outputting data to DQ (Data Input/Output) terminal, comprising: a memory cell array divided into a plurality of banks, each of the banks being precharged and being activated in response to the bank select address signals, each of the banks having a plurality of memory cells arranged in a matrix form, and each of the memory cells being selected in response to address signals; a mode register configured to store an operand code; and a control circuit operable in response to the clock signal, the bank select address signals, the address signals, the inverted Chip Select signal, the inverted Row Address Strobe signal, the inverted Column Address Strobe signal, and the inverted Write Enable signal, the control circuit configured to render the bank select address signals and the address signals to be valid and to set the operand code to the mode register when the inverted Chip Select signal is in a low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, and the inverted Write Enable signal is in the low level and when the clock signal changes, wherein the operand code is issued when all of the banks of the memory cell array are precharged.
 12. The synchronous memory device of claim 11, wherein all of the banks of the memory cell array are precharged when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in a high level, the inverted Write Enable signal is in the low level, and at least one of the address signals is in the high level and when the clock signal changes, and wherein the control circuit renders the bank select address signal to the don't care.
 13. The synchronous memory device of claim 12, wherein the banks of the memory cell array are deactivated to be precharged in response to the bank select address signal when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the high level, the inverted Write Enable signal is in the low level, and at least one of the address signals is in the low level and when the clock signal changes, and wherein the control circuit renders the bank select address to be valid.
 14. The synchronous memory device of claim 11, wherein a row of the memory cell array within the banks is selectively activated in response to the bank select address signal and the row address signal when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in a high level, the inverted Write Enable signal is in the high level and when the clock signal changes, and wherein the control circuit renders the bank select address to be valid and renders the address signal to be a row address signal.
 15. The synchronous memory device of claim 12, wherein a row of the memory cell array within the banks is selectively activated in response to the bank select address signal and a row address signal when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the high level, the inverted Write Enable signal is in the high level, and when the clock signal changes, and wherein the control circuit renders the bank select address signal to be valid and renders the address signal to be a row address signal.
 16. The synchronous memory device of claim 13, wherein a row of the memory cell array within the banks is selectively activated in response to the bank select address signal and a row address signal when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the high level, the inverted Write Enable signal is in the high level, and when the clock signal changes, and wherein the control circuit renders the bank select address signal to be valid and renders the address signal to be a row address signal.
 17. The synchronous memory device of claim 11, wherein: the synchronous memory is operable further in response to /DOM (Data Input/Output Mask signal); the data is output in synchronization with the clock signal and an output of the data is enabled when the Data Input/Output Mask signal is in a high level and the clock signal changes, and the output of the data is disabled when the Data Input/Output Mask signal is in the low level and the clock signal changes; and the control circuit renders the bank select address signals, the address signals, the inverted chip Select signal, the inverted Row Address Strobe signal, the inverted Column Address Strobe signal, and the inverted Write Enable signal to be don't care when the Data Input/Output Mask is asserted.
 18. The synchronous memory device of claim 11, wherein: the synchronous memory is operable further in response to CKE (Clock Enable signal); the data is output in synchronization with the clock signal; and the control circuit suspends input of the clock signal when the Clock Enable is in the low level.
 19. The synchronous memory device of claim 18, wherein during a time when the control circuit suspends the input of the clock signal, an inputting of any command is suspended.
 20. The synchronous memory device of claim 19, wherein a series of data is outputted beginning after a designated latency and ending after a module length of data are output, and wherein the module length is selected from a set of predetermined module length groups.
 21. The synchronous memory device of claim 18, further comprising a refresh control circuit for controlling a refresh operation of the memory cell array, wherein the control circuit interprets the status of control signals as SELF-REFRESH when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, the inverted Write Enable signal is in a high level, and the Clock Enable signal is in the low level and when the clock signal changes, and activates the refresh control circuit.
 22. The synchronous memory device of claim 19, further comprising a refresh control circuit for controlling a refresh operation of the memory cell array, wherein the control circuit interprets the status of control signals as SELF-REFRESH when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, the inverted Write Enable signal is in a high level, and the Clock Enable signal is in the low level and when the clock signal changes, and activates the refresh control circuit.
 23. The synchronous memory device of claim 20, further comprising a refresh control circuit for controlling a refresh operation of the memory cell array, wherein the control circuit interprets the status of control signals as SELF-REFRESH when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in the low level, the inverted Column Address Strobe signal is in the low level, the inverted Write Enable signal is in a high level, and the Clock Enable signal is in the low level and when the clock signal changes, and activates the refresh control circuit.
 24. The synchronous memory device of claim 11, wherein the control circuit renders the address signals to be valid and renders the data in the memory cell array to be read when the inverted Chip Select signal is in the low level, the inverted Row Address Strobe signal is in a high level, the inverted Column Address Strobe signal is in the low level, and the inverted Write Enable signal is in the high level and when the clock signal changes.
 25. The synchronous memory device of claim 24, further comprising an output buffer for outputting the data to Data Input/Output terminal, wherein a series of data is outputted beginning after a designated latency and ending after a module length of data is output and wherein the module length is selected from a set of predetermined module length groups.
 26. The synchronous memory device of claim 25, wherein the module length is variable.
 27. The synchronous memory device of claim 25, wherein the latency is variable. 